The present invention relates to a power semiconductor device, and in particular, relates to a power semiconductor device having high blocking voltage, low thermal resistance, low parasitic resistance, and compact size, and enabling high current performance.
For the purpose of enabling low thermal resistance, low parasitic resistance, compact size, and high current performance, a flip chip structure has been developed, wherein a semiconductor chip is joined to a multilayer substrate not by a wiring, but by a bump or solder. JP-A-10-56131 (description in paragraphs (0020) to (0039)) discloses a semiconductor device, wherein a semiconductor chip is sandwiched between high heat-conductivity insulating substrates, along with an electrode of a semiconductor chip and an electrode pattern of high heat-conductivity insulating substrate are joined by soldering, so as to reduce electric resistance and thermal resistance. Further, it is disclosed that a recession section and a projecting section are mounted on two sheets of high heat-conductivity insulating substrates to be used as a positioning spacer.
JP-A-5-41471 (description of FIGS. 1, 3 and 5) discloses a structure in an air-sealed semiconductor integrated circuit device, wherein, in order to avoid a sealing soldering a package substrate and a cap, a wiring in an inner layer of a multilayer substrate is utilized for a wiring from a CCB bump.